This invention relates to emitter-coupled logic (ECL) circuits.
In a standard ECL circuit as shown in FIG. 1, two switching transistors 12 and 14 are connected at their emitters with the base of switching transistor 14 being connected to a reference voltage. The base of switching transistor 12 is connected to an input voltage. The connected emitters are connected to a current source transistor 24 which provides the current to the two switching transistors. The collectors of emitter-coupled transistors 12, 14 are connected via resistances to a power supply V.sub.cc. An output is obtained at the collector of each switching transistor upon application of an input voltage with one transistor providing a non-inverting output, and the other providing an inverting output. Each output is connected to an emitter follower transistor which isolates the switching transistor's collector from the output. The emitter of each emitter follower is the output and is also connected to a current source transistor.
The reference voltage is referenced to the V.sub.cc supply and is normally generated at a single spot in an ECL integrated circuit and supplied throughout the whole chip via a bus line. Thus, the reference level has a high capacitance associated with it due to the extent of bus routing required. Additionally, the use of a reference voltage requires more power for the circuit.
The V.sub.cc supply voltage can vary due to noise, particularly due to noise generated by a large number of outputs changing states at the same time. Because of the capacitance associated with the reference voltage lines, the reference voltage is slow to respond to noise on the V.sub.cc power supply line. Thus, during dynamic operation of the chip, malfunctions or oscillations can occur due to the V.sub.cc noise.
In addition, because of the noise present on the reference voltage line, the high and low levels used must be sufficiently far apart to provide a margin for such noise. This results in a large voltage swing and thus a slow switching time.
One solution to some of the problems of a reference voltage is shown in an article appearing in the February, 1977 issue of IEEE Journal of Solid-State Circuits, entitled "Improved Feedback ECL Gate with Low Delay-Power Product for the Subnanosecond Region," authored by Hans-Martin Rein and Roland Ranfft which shows an ECL gate without a reference voltage (the "Rein circuit"). The base of the transistor usually connected to a reference voltage is instead coupled to the collector of the input switching transistor. The circuit shown, however, does not include the emitter follower transistors found in an ECL circuit. The Rein circuit is not suitable to drive capacitive loads because of the slow response time due to the collector resistance, R2, limiting the current which can charge a load capacitance.
The need for the reference voltage in the Rein circuit is eliminated by utilizing feedback from the collector of the input transistor to provide the reference voltage level. When the input is low, the input transistor is off and its collector is thus hgh, resulting in a high reference voltage. When the input changes to a high state, the input transistor turns on, simultaneously pulling its collector, and thus the reference voltage, low. Thus, the input will exceed the reference voltage and the transistor will switch states. A drawback, however, is that the high level of the output is reduced due to a voltage drop from current flowing through the collector resistor to the base of the reference transistor. This voltage drop is not present where a reference voltage is used and there is no such connection to the collector resistor. The voltage drop is increased by current flowing into a connected load. The lower high-level voltage makes the circuit more susceptible to noise and thus less reliable.
Noise is even a greater problem where two-level operation of ECL gates is used. In two-level operation, a first level of circuits operate between a logic low and high of given voltages. The second-level circuits operate between different low and high voltages.
An understanding of two-level circuits may be aided by considering the operation of an AND gate in two-level circuits. An AND gate would indicate a logic high only if both inputs were high, and otherwise would indicate a logic low. In two-level operation, the same rules apply except that the logic high of one input is at a different level than the logic high of the other input. Additionally, logic outputs are provided at each voltage level.
Two-level operation requires two reference voltage levels. Thus the problems discussed above for a single reference voltage are doubled. In addition, only two voltage levels are practical with a standard five-volt supply because of the need to provide sufficient separation between the high and low of each level to avoid noise problems.